1. Field of the Invention
The present invention relates to a low-drop (LDO) regulator scheme, and more particularly to an LDO regulator apparatus and a corresponding buffer stage circuit.
2. Description of the Prior Art
Generally speaking, since the size of a power transistor in a conventional LDO regulator circuit is very large, the capacitance value at the gate terminal of the conventional power transistor is also very large. When a loading current flowing through the conventional power transistor changes from a light loading current to a heavy loading current or from the heavy loading current to the light loading current, the voltage level at the gate terminal of the conventional power transistor may not be timely changed due to the large capacitance value. This results in an abrupt voltage change in an output voltage of the conventional LDO regulator circuit. Please refer to FIG. 5, which is a diagram illustrating waveforms of the level V2 at the gate terminal of the conventional power transistor, the output voltage VOUT, and the loading current I. As shown in FIG. 5, when the loading current I changes from a light loading current to a heavy loading current, practically it needs to wait a time period t1 to reduce the level V2 at the gate terminal and cause the level V2 from a high level to reach a low level; the power transistor is a P-type transistor. The time period t1 would cause an abrupt voltage change ΔVUOT1 in the output voltage VOUT which is stable originally. Additionally, when the loading current I changes from the heavy loading current to the light loading current, practically it needs a time period t2 to raise the level V2 at the gate terminal and cause the level V2 from the low level to reach the high level. The time period t2 would cause an abrupt voltage change ΔVUOT2 in the output voltage VOUT which is stable originally. The abrupt voltage changes ΔVUOT1 and ΔVUOT2 result from the large size of the conventional power transistor and the over-low voltage transition rate. It is important to improve the over-low voltage transition rate of the power transistor in the conventional LDO regulator circuit.